Intel Researchers Usher In ‘3-D’ Era In Transistor Design

TOKYO, JAPAN, Sept. 19, 2002 — Intel researchers have developed a three-dimensional (3-D) “tri-gate” transistor design that achieves higher performance with greater power efficiency than traditional planar (flat) transistors. This development provides the first glimpse of a new era of non-planar 3-D transistor designs that Intel and the semiconductor industry must implement to maintain the pace of Moore’s Law beyond this decade.

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