December 6, 2010 — As Intel Corporation prepares to introduce its innovative 2nd Generation Intel® Core™ processor family (formerly codenamed “Sandy Bridge”) early next year, the company’s research and development of future technologies continues unabated. Below is a summary of highlighted papers that Intel will present at the IEEE International Electron Devices Meeting (IEDM) on Dec. 6-8.

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Paper 6.1: Non-Planar, Multi-Gate InGaAs Quantum Well Field Effect Transistors with High-K Gate Dielectric and Ultra-Scaled Gate-to-Drain/Gate-to-Source Separation for Low Power Logic Applications: By M. Radosavljevic, others.

Intel continues to push the forefront of transistor research to ensure the continuation of Moore’s Law. As such, the company is working to shrink future transistors to even smaller sizes so that it can pack more functionality into each processor, while also making them faster and more energy efficient. One very active area of research is in the use of compound semiconductors to form the transistor channel, replacing silicon which is in use for the channel today.

In a paper highlighted by the IEDM, Intel researchers describe compound semiconductor transistors with high-K gate dielectric that are non-planar and hence more amenable to continued shrinking. These devices have:

  • Non-planar, multi-gate Quantum Well Field Effect Transistors (QW-FET) with undoped III-V (InGaAs) channels in the shape of a vertical fin to permit simultaneously higher performance and lower power consumption
  • High-k gate dielectric and a greater enhancement-mode threshold voltage
  • Significantly improved electrostatics

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Paper 6.7: High Mobility Strained Germanium Quantum Well Field Effect Transistor as the P-Channel Device Option for Low Power (Vcc=0.5V) III-V (compound semiconductors) CMOS Architecture: By R. Pillarisetty, others.

The development of future processes requires a large tool box of transistors with a broad choice of materials and structures to choose from for deciding which will scale best for manufacturing faster, denser and more energy-efficient processors. Intel researchers developed P-channel transistors using germanium (Ge) that show the highest hole mobility reported for any Ge device to date. While Ge is not a III-V material, Ge P-channel transistors could potentially be combined with complementary III-V N-channel transistors to form a suitable CMOS architecture. Higher mobility can potentially lead to processors with higher performance and better energy efficiency.

  • This Germanium P-channel Quantum Well Field Effect Transistor (QW-FET) has an architecture that incorporates biaxial strain and minimizes dopant impurity scattering.
  • Parallel conduction in the SiGe buffer was suppressed using a phosphorus junction layer.
  • The Ge QWFET achieves an intrinsic transconductance that is two times higher than the InSb p-channel QWFET.
  • The drive current at fixed Ioff is two times better than the best III-V and Ge devices reported to date.

Further information on the potential of transistors made from III-V materials (compound semiconductors) and the results reported in the above two papers can be found in an Intel blog at http://blogs.intel.com/technology/2010/11/enforcing_moores_law_through_t.php.

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Paper 27.2: RF CMOS Technology Scaling in High-k/Metal Gate Era for RF SoC (System-on-Chip) Applications: By C.-H. Jan, others.

Intel is developing manufacturing process technologies to support a wider range of products beyond traditional microprocessors, including the integration of radio frequency (RF) CMOS devices onto silicon Systems-on-Chip (SoCs). Such integration will lead to more compact and more energy efficient handheld mobile devices. In this paper, Intel describes how it effectively scaled high performance RF CMOS devices from 0.13 µm to the 32 nm generation.

  • The application of novel strained silicon and high-k/metal gate technologies significantly improves RF performance in addition to that of the digital system.
  • The peak cut-off frequency doubles from the 90 nm node to the 32 nm node.
  • Flicker noise is reduced by an order of magnitude relative to the 0.13 µm node.

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Paper 5.2: 25nm 64Gb MLC NAND Technology and Scaling Challenges: By K. Prall and K. Parat.

Intel-Micron describe the advanced technology behind the industry-leading 25nm 64Gb multi-level cell NAND that is currently in production, in an invited paper. High-capacity NAND memory, of course, is of utmost importance as world demand for non-volatile memories grows very rapidly, e.g. in SSDs.

  • Intel-Micron 25nm NAND technology is described.
  • Lithography used is 193nm immersion and uses an advanced pitch reduction technique.
  • The cell size is a mere 0.0028µm2; the half-pitch of the cell is 24.5nm in the word line direction and 28.5nm in the bit line direction.
  • The separation between MLC levels is only 30-50 electrons.
  • Air gap is introduced between the wordlines and bitlines to improve the electrical properties.

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Paper 22.7: Numerical Analysis of Typical STT-MTJ Stacks for 1T-1R Memory Arrays: By C. Augustine, others.

Researchers at Intel describe a numerical study of spin torque transfer magnetic tunneling junction (STT-MTJ) devices that may have applications in the future as embedded memory.

  • Data is stored by the spin orientation of a soft, ferromagnetic material that shows current induced switching.
  • Four types of devices are modeled and their relative merits and demerits for embedded memory applications are evaluated.

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