Intel Foundry於VLSI研討會分享最新製程進展與創新藍圖

A close-up of a brightly colored silicon wafer, displaying a grid pattern. The surface reflects a spectrum of colors, blending from orange on the left to green on the right, showcasing the intricate and reflective nature of the wafer.

Intel 18A, Intel Foundry's leading-edge process node, entered into production in 2025. With RibbonFET and PowerVia, foundry customers are unlocking greater processor scale and efficiency to drive the future of AI computing forward. (Credit: Intel Foundry)

Intel 18A-P已進入風險量產階段,在維持與Intel 18A設計相容的基礎上,提供更高效能、更優異的散熱表現

美國加州聖克拉拉,2026年6月17日–英特爾今(17)日於2026年VLSI研討會上,公布英特爾晶圓代工(Intel Foundry)最新製程藍圖與長期投資的進展,並宣布Intel 18A家族首款效能強化版本Intel 18A-P已正式進入風險量產(Risk Production)階段,依照去年向客戶及合作夥伴公布的時程順利推進。

英特爾執行副總裁暨英特爾晶圓代工總經理Naga Chandrasekaran表示:「我們在VLSI研討會所分享的最新進展,向客戶及合作夥伴再次展現英特爾長期投入先進製程創新的承諾。我們仍有許多工作需要持續推進,但很高興能藉此機會分享Intel 18A-P以及更長期研發計畫的重要進展。」

VLSI研討會分享Intel 18A-P最新進展

透過電晶體、互連技術以及設計技術協同最佳化(Design-Technology Co-Optimization, DTCO),英特爾持續提升Intel 18A-P製程在效能、功耗及設計方面的整體優勢。在VLSI研討會上,英特爾晶圓代工工程團隊公布了以下技術進展:

  • 相較Intel 18A製程,Intel 18A-P在相同功耗下,可提供最高達9%效能提升;或在相同效能下可降低最高18%功耗,同時具備更優異的散熱表現與更大的設計彈性。
  • Intel 18A-P具備最新Power Boost技術,採用全新的雙接點(dual contact)及低電阻電晶體設計,在相同電容下提升驅動電流,進一步提高運作頻率。
  • 透過材料與設計創新,可提升20%~40%的散熱效能。
  • 透過幾何結構與材料最佳化,將晶片層間垂直互連通孔(Via)電阻降低10%~30%,提升訊號傳輸效率。
  • 透過PMOS應變工程提升載子遷移率(Mobility),讓電流更有效率地通過電晶體。
  • 提供全新低功耗及高效能電晶體選項,以滿足不同產品設計需求。
  • 於超低臨界電壓(Ultra Low Voltage Threshold,ULVT)與低臨界電壓(Low Voltage Threshold,LVT)之間,新增第五組邏輯臨界電壓(Vt),提供設計人員更多速度與功耗最佳化的平衡空間。
  • Intel 18A-P與Intel 18A之設計規則完全相容,可直接沿用既有IP與設計流程,加速產品開發。
  • 與Intel 18A相同,Intel 18A-P提供180奈米與160奈米兩種標準元件高度,以及50奈米的接觸式多晶矽閘極間距(Contacted Poly Pitch)。

VLSI研討會其他重要進展

英特爾去年率先於Intel 18A製程導入環繞式閘極(Gate-All-Around,GAA)電晶體與背面供電技術。本週於VLSI研討會上,進一步說明這兩項核心技術如何為未來邏輯晶片提供更高效能、更佳能源效率及持續微縮能力奠定基礎:

  • 在VLSI研討會特邀演講中,英特爾晶圓代工副總裁暨院士Eric Karl展示英特爾如何量化背面供電與環繞式閘極電晶體所帶來的技術優勢。他指出相較於傳統正面供電互連架構,此技術可減少11%的佈線面積,並將動態電壓驟降減少達10倍,進而實現最高6%的頻率提升,或降低超過15%的動態功耗。
  • 英特爾晶圓代工矽與平台工程事業群Manju Shamanna分享採用環繞式閘極電晶體與背面供電技術打造的CPU核心實測成果。結果顯示,在較低工作電壓下可獲得更優異的頻率擴展能力,包括在約5V的低電壓環境下提升30%運作頻率,同時降低供電電壓損失(IR Drop),並進一步提升整體運作效率。

未來創新研發成果

英特爾亦於會中分享多項長期研發成果,聚焦未來半導體持續微縮的重要技術方向:

  • 互補式場效電晶體(Complementary FET,CFET):英特爾展示採用45奈米閘極間距、由NMOS與PMOS元件垂直堆疊構成的單晶式CFET反相器。透過垂直元件架構,為環繞式閘極電晶體之後的邏輯製程持續微縮提供新的技術發展方向。
  • 氮化鎵(GaN)與矽(Si)整合電源管理技術:英特爾展示在300毫米的晶圓上,將氮化鎵功率元件與矽邏輯電路進行整合,其中包含約1,000個邏輯閘數位控制模組,可在單一製程整合高效能功率元件與大規模數位控制電路,降低系統複雜度。
  • 減材釕(Subtractive ruthenium)互連技術:英特爾展示結合氣隙(Air Gap)整合技術的減材釕互連,相較於傳統銅互連,可將電容降低最高達35%,並帶來可量測的頻率提升。隨著互連線持續微縮,這項技術為改善電阻電容特性與互連微縮提供了一條具發展潛力的技術路徑。

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  • Our Intel 18A-P process node and risk production of such node, including the performance, power and design benefits, competitiveness and technological advancements;
  • Our research developments in CFET inverters, GaN + Si Integration and sRu interconnects.

Such statements involve many risks and uncertainties that could cause our actual results to differ materially from those expressed or implied, including those associated with:

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  • the complexities and uncertainties in developing and implementing new semiconductor products and manufacturing process technologies;
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 關於英特爾

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