Intel Secure Enclave: Securing High-Performance Computing at the Tactical Edge

By: Gena Gleason, senior director and general manager of Intel Government Technologies, Foundry Segment.

The Limits of Legacy Approaches

For decades, defense and aerospace systems have relied on architectures that were not designed for today’s data intensity. Analog-heavy signal-processing chains, while effective in earlier generations of radar and sensing systems, pose inherent limitations on scalability, flexibility, and efficiency. As sensor resolution increases, particularly in applications such as phased array radar and infrared imaging, the volume of data grows exponentially, placing unsustainable demands on both processing and power.

At the same time, these systems must operate within fixed SWaP (size, weight, and power) operational limits. In aircraft, power is a shared and finite resource, with competing subsystems drawing from the same limited supply, making it the most constrained resource on the platform.

In space-based systems, the challenge is even more acute: power generation is hampered, and thermal dissipation is intrinsically difficult in vacuum environments where conventional cooling methods are unavailable.

These realities expose the limits of legacy semiconductor technologies and architectures. Many current deployments are still built on mature process nodes that cannot deliver the efficiency or density required to scale performance. As a result, system designers must either sacrifice capability to remain within power and thermal envelopes or accept increased latency by offloading processing elsewhere – constraining overall mission effectiveness.

A Shift to Digital, Edge-Native Architectures

The path forward lies in a transition to fully digital, edge-native architectures that can process data where it is generated, closer to the sensor.

Moving from analog to digital signal processing unlocks significant gains in performance, flexibility, and integration. All-digital radar systems reduce bandwidth requirements (by triggering alerts without transmitting full datasets) and detect increasingly subtle signals at the pixel level – from distant objects in radar systems to early indicators of launches in space-based infrared sensors.

While this shift is consistent across domains—including space, air, land, naval, and cyber—the implementation varies based on mission and environment, from radiation and thermal constraints in space-based systems to the power availability and stability of terrestrial and data center deployments.

Precision at Scale: The Sensor Challenge

The next challenge emerges at the sensor itself: scaling resolution without exceeding power and thermal limits.

Moving from analog-based architecture to all-digital pixels reduces pixel size, allowing for greater pixel density and higher resolution. But increasing pixel density drives a corresponding rise in processing demand, placing additional strain on power budgets and thermal limits.

Innovations in digital pixel architecture are helping to resolve this challenge. By enabling both pixel miniaturization and lower per-pixel power consumption, these approaches allow systems to scale resolution without exceeding SWaP limits. Additionally, integrating processing capabilities directly into the sensor layer enhances sensitivity and enables faster, more accurate detection, improving both precision and mission responsiveness.

Intel 18A: Enabling a New Class of Edge Performance and Expanded Operational Capability

Advances at the process technology level are critical to making these architectural shifts possible. Intel 18A represents a significant step forward, delivering improvements in performance, power efficiency, and density that are particularly well-suited to SWaP-constrained environments.

Compared to Intel 16 process technologies, Intel 18A can deliver 5x the power efficiency, or double the performance, and up to 10x reduction in area. These gains translate directly into system-level benefits: more processing capability within the same power envelope, reduced size and weight, and greater flexibility to integrate additional mission functions.

Equally important are innovations beyond the transistor. Advanced packaging technologies, such as 2.5D and 3D integration, enable heterogeneous systems that combine multiple chiplets, potentially from different process nodes, into a single package. These capabilities allow designers to cost optimize and integrate the best technologies for each using leading edge process nodes for critical functions and older nodes for less critical functions, whether from Intel or third-party sources, into a unified, SWaP-optimized system.

In many cases, packaging becomes as critical as the underlying silicon in determining overall system performance, cost efficiency, and design flexibility.

However, increasing levels of power density and temperature driven leakage power loss are expected to limit gains in performance and power efficiency. In order to overcome package thermal limitation, Intel investigated a class of high-performance Integrated Heat Spreaders (IHS) that can enable liquid cooling with an estimated efficacy of at least 2x more than state of the art Air cooled solutions. Additional objectives of the high performance IHS solutions include reliability, testability, and serviceability at system level. In addition to liquid cooling in IHS, Intel offers multiple TIM (Thermal Interface Material) options to reduce thermal resistance inside package.

Together, these advances form the foundation for a new generation of edge systems capable of processing vast data streams in real time, without exceeding the bounded conditions of their operating environments.

From Innovation to Deployment: Overcoming Adoption Challenges

Transitioning to advanced-node technologies is not without its challenges. Designing for new architectures, such as gate-all-around transistors and backside power delivery, requires new tools, methodologies, and expertise. Development cycles for custom silicon can span years, and cost and schedule remain top priorities for defense and aerospace programs, often outweighing performance considerations in determining adoption timelines.

However, these challenges are consistent with any shift to leading-edge technology. With the right design enablement, ecosystem support, and modular approaches such as chiplet-based design, defense agencies can accelerate adoption while managing risk. Early engagement is key, particularly as advanced-node design cycles extend beyond traditional timelines.

Securing the Edge: The Role of U.S.-Based Secure Manufacturing Capability

As advanced microelectronics become increasingly central to national security, where and how they are manufactured is as critical as their technical capabilities. Growing geopolitical threats and reliance on these technologies have elevated supply chain security to a strategic priority.

In response, the U.S. government has called for a fully domestic, secure capability to produce state-of-the-art microelectronics. Intel is supporting this effort through its work with the Department of the Air Force to develop and manage the Secure Enclave program.

Secure Enclave is a protected overlay in Intel’s commercial manufacturing environment – Intel Foundry – that enables domestic, secure production of sensitive and mission-critical microelectronics spanning design, fabrication, and advanced packaging, delivering a uniquely comprehensive, secure manufacturing capability.

Secure Enclave also builds on prior government microelectronics initiatives such as Rapid Assured Microelectronics Prototypes (RAMP), Rapid Assured Microelectronics Prototypes Commercial (RAMP-C), and State-of-the-art Heterogeneous Integrated Packaging (SHIP). These U.S. programs create a model of cooperation that allied governments and international partners could adopt to help ensure resilient, supply chains.

The result is a unique capability: the ability to develop and deploy state-of-the-art microelectronics for mission-critical systems without compromising on security or supply chain resilience.

Enabling Decision Advantage at the Edge

The convergence of data growth, operational constraints, and evolving mission requirements is reshaping the landscape of edge computing. Systems must deliver greater capability within fixed physical and operational limits. Meeting these demands requires a holistic approach that spans process technology, system architecture, packaging, and secure manufacturing.

Intel 18A, combined with advanced packaging and Secure Enclave capabilities, provides a foundation for addressing these challenges. By enabling ultra-efficient, high-performance processing at the edge and ensuring that these capabilities are delivered through a secure, domestic supply chain, Intel is helping to unlock faster, more accurate insights where they matter most.

In mission-critical environments, where decisions must be made in real time and under uncertainty, that capability is more than a technical advantage. It is a decisive one.